module sequence_wait ();

logic a, b, c, d, e;
logic clk = 0;

// 在时钟上升沿检测
// 要求连续三个时钟周期分别检测到a、b、c信号为高
// 即：第一个周期a=1，第二个周期b=1，第三个周期c=1
sequence abc; 
    @(posedge clk) a ##1 b ##1 c; 
endsequence 

// 在时钟下降沿检测
// 范围延迟操作符 ##[2:5]，要求信号d为高，然后经过2到5个时钟周期后e信号为高
sequence de; 
    @(negedge clk) d ##[2:5] e; 
endsequence 

initial begin 
    forever begin
        // .triggered是SystemVerilog序列的特殊属性，当序列完全匹配时为真
        // 暂停执行直到任一序列完成匹配
        wait (abc.triggered || de.triggered); 
        if (abc.triggered) begin
            $display( "@%g abc succeeded", $time ); 
        end
        if (de.triggered) begin
            $display( "@%g de succeeded", $time );
        end
        #2;
    end
end

// Testbench code
initial begin
    $monitor("@%g\tclk: %b a %b b %b c %b d %b e %b", $time, clk, a, b, c, d, e); 
    repeat (2) begin
        #2 a = 1; d = 1;
        #2 b = 1; e = 1;
        #2 c = 1;
        #2 a = 0;
        b = 0; c = 0; e = 0;
    end
    #2 $finish;
end

always #1 clk = ~clk;

endmodule // sequence_wait 
